一、課程說明(Course Description)
<br>The course is to teach students how to model digital design 
<br>with hardware description languages (Verilog and VHDL), and how to use commercial CAD tools (e.g., Candence Verilog-XL, Synopsys Design Compiler) for simulation and synthesis.
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<br> 二、指定用書(Text Books)
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<br>Nazeih M. Botros, HDL Programming Fundamentals: VHDL and Verilog, 2006 (ISBN: 1-58450-855-8)
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<br> 三、參考書籍(References)
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<br>Michael D. Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, 1999.
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<br>Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, 2003.
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<br> 四、教學方式(Teaching Method)
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<br>Lectures and discussions
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<br> 五、教學進度(Syllabus)
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<br>Part I: Verilog 
<br>  - Introduction                                          
<br>  - Data-flow descriptions
<br>  - Behavioral descriptions
<br>  - Structural descriptions
<br>  - Switch-level descriptions
<br>  - Tasks and functions
<br>  - Advanced descriptions
<br>  - Synthesis 
<br>  - Design examples
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<br>Part II: VHDL bascis 
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<br>Part III: Advanced topics
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<br> 六、成績考核(Evaluation)
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<br>Homework: 50%
<br>Midterm Exam: 25%
<br>Final Exam: 25%
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<br> 七、可連結之網頁位址
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<br>http://vlsicdb.cs.nthu.edu.tw/~lab221/course/cs4120/cs4120.html
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<br>(Last updated on 2/17/2008)
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