一、課程說明(Course Description)
This course provides the fundamental knowledge of designing Very
Large-Scale Integrated circuits (VLSI). The coverage includes both
the full-custom design style as well as the cell-based synthesis flow.
It begins with a review of the IC fabrication process and the CMOS
transistor theory. Then, the layout rules and design techniques for
a variety of CMOS logic circuits such as inverters, logic gates,
flip-flops, and arithmetic circuits using different design styles
(e.g., static logic, steering logic, and dynamic logic) are discussed.
For system-level design, low-power techniques, semiconductor memories,
will be discussed in detail.
二、指定用書(Text Books)
Neil H. E. Weste and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3nd Ed.,
Addison Wesley, 2005.
三、參考書籍(References)
1. Jan M. Rabaey, Digital Integrated Circuits, 2nd Ed., Prentice Hall, 2003
四、教學方式(Teaching Method)
Lecture by LCD Porjection
五、教學進度(Syllabus)
1. Introduction
2. Fabrication Process
3. MOS Transistor Theory
4. Circuit Characterization and Performance Estimation
5. CMOS Circuit and Logic Design
6. CMOS Design Methods
7. CMOS Subsystem Design
8. Low Power Design Techniques
六、成績考核(Evaluation)
Homework : 45% (No delay!)
Exam : 40% (Midterm 20% + Final 20%)
Final Project: 15%
七、可連結之網頁位址
EE5250 VLSI Design