一、課程說明(Course Description)
The course is to teach students how to model digital design
with hardware description languages (Verilog and VHDL), and how to use commercial CAD tools for simulation and synthesis.
二、指定用書(Text Books)
Ming-Bo Lin, Digital System Designs and Practices Using Verilog HDL and FPGAs, John Wiley & Sons, 2008.
三、參考書籍(References)
Michael D. Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, 1999.
Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, 2003.
四、教學方式(Teaching Method)
Lectures and discussions
五、教學進度(Syllabus)
Part I: Verilog
- Introduction
- Simulation
- Structural modeling
- Dataflow modeling
- Behavioral modeling
- Tasks and functions
- Synthesis
- Design examples
Part II: VHDL bascis
六、成績考核(Evaluation)
Homework: 50%
Midterm Exam: 25%
Final Exam: 25%
七、可連結之網頁位址