一、課程說明(Course Description)
This course provides the fundamental knowledge of designing Very Large-Scale
Integrated circuits (VLSI). It begins with a review of the IC fabrication
process and the CMOS transistor theory. Then, the layout rules and design
techniques for a variety of CMOS logic circuits such as inverters, logic gates,
flip-flops, and arithmetic circuits using different design styles (e.g., static
logic, steering logic, and dynamic logic) are discussed. For system-level
design, low-power techniques, semiconductor memories, and IO plan will be
discussed in detail.

二、指定用書(Text Books)

Neil H. E. Weste and David Harris, CMOS VLSI Design: A Circuits and Systems
Perspective, 3nd Ed.,
Addison Wesley, 2005.

三、參考書籍(References)

1. Jan M. Rabaey, Digital Integrated Circuits, 2nd Ed., Prentice Hall, 2003

四、教學方式(Teaching Method)

Lecture by LCD Porjection

五、教學進度(Syllabus)

Week 1-2 : Introduction
Week 3 : CMOS Processing Technology
Week 4 : MOS Transistor Theory
Week 5-7 : Circuit Characterization and Performance Estimation
Week 8-9 : Combinational Circuit Design
Week 10-11 : Sequential Circuit Design
Week 12-13 : Design Methodology and Tools
Week 14-15 : Datapath Subsystem
Week 16 : Array Subsystem
Week 17 : Special-Purpose Subsystem

六、成績考核(Evaluation)

Homework : 30% (No delay!)
Exam : 60% (Midterm 25% + Final 35%)
Final Project: 10%

七、可連結之網頁位址