一、課程說明(Course Description)
<br>This course will introduce students to electronic design automation (EDA), or 
<br>called CAD for VLSI.  The field is very broad and hence cannot be covered in
<br>a single course. Therefore, we choose to give an introduction and concentrate on 
<br>high level synthesis. The physical design automation portion has been spin-off 
<br>as an independent course by Professor Ting-Gee Wang.
<br>This course is suitable for EE or CS graduate students who are interested in a 
<br>career in the IC design or CAD industry.
<br>. Brief review of VLSI design process
<br>  . Design capturing using Verilog Hardware Description Language
<br>  . Simulation for Functional Verification
<br>  . Synthesis into Gate Level Design
<br>  . DFT - Design for Testability
<br>  . Layout - Physical Implementation including Placement and Routing
<br>  . Verification - Post Layout Design Rule and Timing Verification 
<br>  . Co-design
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<br>. High Level Synthesis
<br>  . Description languages
<br>  . Architecture and modeling
<br>  . Scheduling
<br>  . Allocation
<br>  . Control generation
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<br>. Machine Problems
<br>  . Please see http://lin.cs.nthu.edu.tw for detail
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<br>This course consists of three portions:
<br>  I. Lectures by the professor
<br>  II. Student presentations of selected important papers in high level synthesis
<br>  III. Student presentation of their machine problems
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<br> 二、指定用書(Text Books)
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<br>High Level Synthesis -- Gajski, Dutt, Wu and Lin
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<br> 三、參考書籍(References)
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<br>Papers from ICCAD, DAC, ACM TODAES, IEEE T VLSI, and IEEE T on CAD
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<br>Past problem sets from National CAD Contest
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<br> 四、教學方式(Teaching Method)
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<br>Lecturing and Discussion
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<br>This course consists of three portions:
<br>  I. Lectures by the professor
<br>  II. Student presentations of selected important papers in high level synthesis
<br>  III. Student presentation of their machine problems
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<br> 五、教學進度(Syllabus)
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<br> 六、成績考核(Evaluation)
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<br>Two Machine problems 25% each
<br>Project 50%
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<br> 七、可連結之網頁位址
<br>http://lin.cs.nthu.edu.tw
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