一、課程說明(Course Description)
<br>The course is to teach students how to model digital design 
<br>with hardware description languages (Verilog), and how to use commercial CAD tools for simulation and 
<br>synthesis.
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<br> 二、指定用書(Text Books)
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<br> 三、參考書籍(References)
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<br>Michael D. Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, 1999.
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<br>Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, 2003.
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<br>Ming-Bo Lin, Digital System Designs and Practices Using Verilog HDL and FPGAs, John Wiley & Sons, 2008. 
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<br> 四、教學方式(Teaching Method)
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<br>Lectures and discussions
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<br> 五、教學進度(Syllabus)
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<br>Verilog 
<br>  - Introduction 
<br>  - Simulation
<br>  - Structural modeling                                         
<br>  - Dataflow modeling
<br>  - Behavioral modeling
<br>  - Tasks and functions
<br>  - Synthesis 
<br>  - Design examples
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<br> 六、成績考核(Evaluation)
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<br>Homework + Class Participation: 50%
<br>Midterm Exam: 25%
<br>Final Project: 25%
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<br> 七、可連結之網頁位址
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<br>http://nthucad.cs.nthu.edu.tw/~cthuang/ 
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