一、課程說明(Course Description)
This course provides the fundamental knowledge of testing Very
Large-Scale Integrated circuits (VLSI). The emphasis is on the
Computer-Aided-Design (CAD) algorithms as well as the Design-For-Testability
(DFT) techniques. It begins with the topics of fault modeling and fault
simulation, followed by the algorithms of Automatic Test Pattern Generation
(ATPG). Next, the popular Design-for-Testability (DFT) techniques, such as
Scan Methodology and Built-In Self-Test (BIST) for logic and memory will be
introduced. Upon completion, the students will master the man.
二、指定用書(Text Books)
三、參考書籍(References)
l M. Abramovici, M. A. Breuer, and A. D. Friedman, “Digital System Testing and
Testable Design”, 2nd edition, Institute of Electrical Engineering, ISBN:
0780310624, (Jan. 1998)
2. P. K. Lala,“Digital Circuit Testing and Testability”, Academic Press,
國內代理: 滄海書局 (1997).
3. Stanley L. Hurst, “VLSI Testing: Digital and Mixed Analogue/Digital
Techniques’, INSPEC Incorporated, ISBN: 0852969015, (Feb. 1999).
四、教學方式(Teaching Method)
lecture with slides
五、教學進度(Syllabus)
Table of Contents
Introduction
Simulation and Fault Model
Automatic Test Pattern Generation (ATPG)
Design-for-Testability (DFT)
Built-In Self-Test (BIST)
IC Diagnosis
ATPG-Based Logic Synthesis and Verification
Mixed Signal Testing and DFT
六、成績考核(Evaluation)
Homework 20%, Midterm Exam. 40%, and Final Project 40%
七、可連結之網頁位址