*課程說明(Course Description)
In this course, students will learn the basics knowledge of IC designs, focus on transitor-level circuits and chip-level designs methdology. You will also get familiar with the transitor-level IC-related CAD tools (design, simulation, layout, RC-extraction) after finishing all the assigned homeworks and project. This course targes at both "知識學習"與"動手做".
*教學方式(Teaching Method)
Lectures with power-point files (Mondays, 13:00-15:10, at assigned classroom)
Embedded Labs (Tutorial + TA hours) (Thursdays, 13:00-14:00, at EE Workstation Room, strating from 2nd or 3rd week)
*教學進度(Syllabus)
1. Introductions
2. CMOS Devices and IC Process
3. Static and Dynamic CMOS Gates (Combination Logics)
4. Sequential CMOS Circuits
5. Interconnects and Parasitic effects
6. Memory and Array Structures
7. Chip Design Methodologies
8. Chip-level Optimizations
9. Issues in Nano-scale IC
* IC Design CAD Tools
1. HSPICE
2. Schematic Entry (Cadence-Composer)
3. Layout (Laker)
4. DRC/LVS (Calibre)
5. RC extraction (Calibre)
*成績考核(Evaluation: 50% exam, 50% practice)
2 Midterm exams: 35% (1st: 20%, 2nd: 15%)
1 Final Exam.: 15%
5 Homeworks (Labs): 30% (6% each)
1 Design Project (2 students per team): 20%
建議先修課程 (Suggested Course prerequisites):
1. Electronics (電子學)
2. Logic Designs (邏輯設計)
Text Book
1.“Digital Integrated Circuits: A Design Perspective” by Rabaey
2. IEEE Papers (ISSCC and IEEE JSSC)
Important Note:
1. Lecture/Lab classes start from 13:00, 20min earlier than regular class schedule.
2. Tutorial on "how to use CAD tools and Q&A for homeworks" will be given on Thursdays (13:00-14:10).
3. Addtional TA hours in the evening (2 hours per week) will be available at EE Workstation Room
4. Limited number of seats are availabe (原則上不加簽). If you cannot commit spending effort to finish project/homeworks, please leave the seats to other students who are willing to commit.