*課程說明(Course Desc<x>ription)
<br>
<br>In this course, students will learn the basics knowledge of IC designs, focus on transitor-level circuits and chip-level designs methdology. You will also get familiar with the transitor-level IC-related CAD tools (design, simulation, layout, RC-extraction) after finishing all the assigned homeworks and project. This course targes at both "知識學習"與"動手做".
<br>
<br>
<br>*教學方式(Teaching Method)
<br>
<br>Lectures with power-point files (Mondays, 13:00-15:10, at assigned classroom)
<br>em<x>bedded Labs (Tutorial + TA hours) (Thursdays, 13:00-14:00, at EE Workstation Room, strating from 2nd or 3rd week)
<br>
<br>*教學進度(Syllabus)
<br> 
<br>1. Introductions
<br>2. CMOS Devices and IC Process
<br>3. Static and Dynamic CMOS Gates (Combination Logics)
<br>4. Sequential CMOS Circuits
<br>5. Interconnects and Parasitic effects
<br>6. Memory and Array Structures
<br>7. Chip Design Methodologies
<br>8. Chip-level Optimizations
<br>9. Issues in Nano-scale IC
<br>
<br>* IC Design CAD Tools
<br>1. HSPICE
<br>2. Schematic Entry (Cadence-Composer)
<br>3. Layout (Laker)
<br>4. DRC/LVS (Calibre)
<br>5. RC extraction (Calibre)
<br>
<br>*成績考核(Evaluation: 50% exam, 50% practice)
<br>2 Midterm exams: 35% (1st: 20%, 2nd: 15%)
<br>1 Final Exam.: 15%
<br>5 Homeworks (Labs): 30% (6% each)
<br>1 Design Project (2 students per team): 20% 
<br>
<br>建議先修課程 (Suggested Course prerequisites):
<br>1. Electronics (電子學) 
<br>2. Logic Designs (邏輯設計)
<br> 
<br>Text Book
<br>1.“Digital Integrated Circuits: A Design Perspective” by Rabaey
<br>2. IEEE Papers (ISSCC and IEEE JSSC)
<br>
<br>Important Note:
<br>1. Lecture/Lab classes start from 13:00, 20min earlier than regular class schedule.
<br>2. Tutorial on "how to use CAD tools and Q&A for homeworks" will be given on Thursdays (13:00-14:10).
<br>3. Addtional TA hours in the evening (2 hours per week) will be available at EE Workstation Room
<br>4. Limited number of seats are availabe (原則上不加簽). If you cannot commit spending effort to finish project/homeworks, please leave the seats to other students who are willing to commit.
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>
<br>