一、課程說明(Course Desc<x>ription)
<br>This course provides the fundamental knowledge of designing Very Large-Scale 
<br>Integrated circuits (VLSI). It begins with a review of the IC fabrication 
<br>process and the CMOS transistor theory. Then, the layout rules and design 
<br>techniques for a variety of CMOS logic circuits such as inverters, logic 
<br>gates, flip-flops, and arithmetic circuits using different design st<x>yles (e.g., 
<br>static logic, steering logic, and dynamic logic) are discussed. For system-level 
<br>design, low-power techniques, semiconductor memories, and IO plan will be 
<br>discussed in detail.
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<br> 二、指定用書(Text Books)
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<br>Neil H. E. Weste and David Harris, CMOS VLSI Design: A Circuits and Systems 
<br>Perspective, 4th Ed., Addison Wesley,  2010.
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<br> 三、參考書籍(References)
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<br>1. Jan M. Rabaey, Digital Integrated Circuits, 2nd Ed., Prentice Hall,  2003
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<br> 四、教學方式(Teaching Method)
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<br>Lecture by LCD Porjection
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<br> 五、教學進度(Syllabus)
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<br>Week 1-2          : Introduction
<br>Week 3            : CMOS Processing Technology
<br>Week 4            : MOS Transistor Theory
<br>Week 5-7          : Circuit Characterization and Performance Estimation
<br>Week 8-9          : Combinational Circuit Design
<br>Week 10-11        : Sequential Circuit Design
<br>Week 12-13        : Design Methodology and Tools
<br>Week 14-15        : Datapath Subsystem
<br>Week 16           : Array Subsystem
<br>Week 17           : Special-Purpose Subsystem
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<br> 六、成績考核(Evaluation)
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<br>Homework      :  25% (No delay!)
<br>Exam          :  55% (Midterm 25% + Final 30%)
<br>Final Project :  20%
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<br> 七、可連結之網頁位址
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