This course is to let students have hand-on experiences of modern

digital designs with the following topics:

- Introduction to the basic concepts in logic design that form the basis of digital computation and

communication systems.

- Verilog and FPGA implementations.

- Logic gates and memory elements.

- Timing methodologies. Finite state systems.

- Programmable logic.

- Basic computer organization.

二、指定用書 (Textbook)

There is no required textbook. However, we will provide the lecture

notes. In addition, the students need to possess backgrounds of basic

logic design concepts.

Prerequisite: Digital Logic Design or VLSI design.

三、參考書籍 (References)

- S. Palnitkar, Verilog HDL A guide to Digital Design and Synthesis (Second

Edition), Pearson Education Taiwan Ltd.

- Programmable Logic Design Quick Start Handbook, Xilinx Inc.

http://www.xilinx.com

- ISE Quick Start Tutorial

http://toolbox.xilinx.com/docsan/xilinx6/books/docs/qst/qst.pdf

四、教學方式 (Teaching Method)

Lectures and labs

Lab:

The students will have opportunity to write Verilog codes and test their

design on FPGA boards. The regular lab time is 3:30pm~5:20pm, Thursdays.

Lectures:

The instructor will teach Verilog as well as basic concepts of Logic

Design, VLSI Design, Computer Architectures, as well as backgrounds on

programming and hardware implementation knowledge.

五、教學進度(Syllabus)

1: Gate-level modeling

2: Data-flow modeling and Behavioral modeling

3: Sequential circuits & FPGA board

4: Finite State Machines & FPGA board

5: Advanced circuit implementation, Finite State Machine, and FPGA board

6: Short-term project

Final Project: The students will submit a proposal, then exercise their creativity to

build a small course project.

六、成績考核(Evaluation)

To be announced.

七、可連結之網頁位址

To be announced.