深度學習硬體加速器設計

Time: 3:30-6:20 pm, Thursday (R7R8R9)
Place: Room 107, Delta Building
Instructors:
Youn-Long Lin (Two thirds)
Albert Liu (One third), CEO Kneron

Intended Students:
CS Graduate Students or Undergraduate students in their 3rd, or 4th year

objectives:
To teach students theory, algorithms, Python programming, Verilog
implementation, and ASIC optimization of contemporary neural networks in terms
of performance, accuracy, model size, energy efficiency

Prerequisites:
Digital Logic Design and Hardware Lab
Computer Architecture
Familiar with Synthesizable Verilog

Reference:
Selected papers
Handouts

Grading:
Machine problems
Paper presentation
Term Project
Final Presentation

Week Date Topics Instructor
1 2/21 Multi layer Perceptron Lin
2 2/28 Holiday No meeting
3 3/7 Convolutional Neural Networks Lin
4 3/14 Famous Networks: LeNet, AlexNet, ResNet, DenseNet
Lin
5 3/21 HW Accelerator – Eyerise, Cambricon Lin
6 3/28 Model Compression – Hang Song’s Work Lin
7 4/4 Holiday No meeting
8 4/11
9 4/18 Memory Computing and fast IO Chunchen
10 4/25 Reconfigurable Neural Network
-Convolution Filter Decomposition Technique (layer Level Reconfiguration)
Chunchen
11 5/2
12 5/9
13 5/16 Accelerators for Cloud Training - Example
accelerators: - TPU (Google's Tensor Processing Unit), Wave computing
Chunchen
14 5/23 Convolutional Neural Network operation device
Chunchen
15 5/30
16 6/7 Accelerators for Inference: - Example accelerators: -
Kneron, Minerva Chunchen
17 6/14
18 Final Exam Week