一、課程說明(Course 
<br>Desc<x>ription)
<br>This course provides the 
<br>fundamental knowledge of 
<br>designing Very Large-Scale 
<br>Integrated circuits (VLSI). It 
<br>begins with a review of the IC 
<br>fabrication 
<br>process and the CMOS transistor 
<br>theory. Then, the layout rules 
<br>and design 
<br>techniques for a variety of CMOS 
<br>logic circuits such as inverters, 
<br>logic 
<br>gates, flip-flops, and arithmetic 
<br>circuits using different design 
<br>st<x>yles (e.g., 
<br>static logic, steering logic, and 
<br>dynamic logic) are discussed. For 
<br>system-level 
<br>design, low-power techniques, 
<br>semiconductor memories, and IO 
<br>plan will be 
<br>discussed in detail.
<br>
<br> 二、指定用書(Text Books)
<br>
<br>Neil H. E. Weste and David 
<br>Harris, CMOS VLSI Design: A 
<br>Circuits and Systems 
<br>Perspective, 4th Ed., Addison 
<br>Wesley,  2010.
<br>
<br> 三、參考書籍(References)
<br>
<br>1. Jan M. Rabaey, Digital 
<br>Integrated Circuits, 2nd Ed., 
<br>Prentice Hall,  2003
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<br> 四、教學方式(Teaching Method)
<br>
<br>Lecture by LCD Porjection
<br>
<br> 五、教學進度(Syllabus)
<br>
<br>Week 1-2          : Introduction
<br>Week 3            : CMOS 
<br>Processing Technology
<br>Week 4            : MOS 
<br>Transistor Theory
<br>Week 5-7          : Circuit 
<br>Characterization and Performance 
<br>Estimation
<br>Week 8-9          : Combinational 
<br>Circuit Design
<br>Week 10-11        : Sequential 
<br>Circuit Design
<br>Week 12-13        : Design 
<br>Methodology and Tools
<br>Week 14-15        : Datapath 
<br>Subsystem
<br>Week 16           : Array 
<br>Subsystem
<br>Week 17           : Special-
<br>Purpose Subsystem
<br>
<br> 六、成績考核(Evaluation)
<br>
<br>Homework      :  25% (No delay!)
<br>Exam          :  55% (Midterm 25% 
<br>+ Final 30%)
<br>Final Project :  20%
<br>
<br> 七、可連結之網頁位址
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