一、課程說明 (Course Desc<x>ription)
<br>   Introduction to the basic concepts in logic design that form the basis of 
<br>computation and communication circuits. Verilog and FPGA implementations. Logic 
<br>gates and memory elements. Timing methodologies. Finite state systems. 
<br>Programmable logic. Basic computer organization.
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<br>二、指定用書 (Text Books)
<br>   There is no required textbook.  However, the students need to possess 
<br>backgrounds of basic logic design concepts.  
<br>   
<br>   Prerequisite: Logic Design or VLSI design.
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<br>三、參考書籍 (References)
<br>   Digital Design with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank 
<br>Vahid.
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<br>四、教學方式 (Teaching Method)
<br>   Lab: The students will have opportunity to write Verilog codes and test their 
<br>design on FPGA boards.  The regular lecture and lab time are 3:30pm~5:20pm (Tue) 
<br>and 3:30pm~5:30pm (Thu), respectively.
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<br>   Lectures: The instructor will teach Verilog as well as basic concepts of 
<br>Logic Design, VLSI Design, Computer Architectures, as well as backgrounds on 
<br>programming and hardware implementation knowledge.
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<br>五、教學進度 (Syllabus)
<br>   Lab 1: Gate-level modeling
<br>   Lab 2: Data-flow modeling and Behavioral modeling
<br>   Lab 3: Sequential circuits & FPGA board
<br>   Lab 4: Finite State Machines & FPGA board
<br>   Lab 5: Advanced circuit implementation, Finite State Machine, and FPGA board
<br>   Lab 6: Short-term project
<br>   Final Project: The students will submit a proposal, then exercise their 
<br>creativity to build a small course project.
<br>
<br>六、成績考核 (Evaluation)
<br>   Six lab assignments: 45%
<br>   One final project: 20%
<br>   One mid-term quiz: 10%
<br>   One final-term quiz: 15%
<br>   Presentation: 10%
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<br>七、可連結之網頁位址
<br>   To be available soon