Digital Signal Processing Integrated Circuits Design (COM524000)
<br>
<br>Course Desc<x>ription
<br>
<br>This course introduces both the theory and practice for designing&#160;a digital 
<br>signal 
<br>processing IP for various systems. The first part is to introduce&#160;the theoretic 
<br>tools&#160;to design the digital signal processing architecture. Besides, the noise 
<br>and 
<br>power issues for communication are also&#160;introduced when the architecture is 
<br>implemented in fixed-point signal format&#160;for VLSI.&#160;In the second part, the 
<br>circuit-ba<x>sed energy delay model&#160;are also introduced&#160;to design the hardware 
<br>architecture according to&#160;different constraints including timing, cost, power, 
<br>etc. The third&#160;part will provide some DSP architectures, including arithmetic 
<br>operator architecture, FIR/IIR filter, multi-rate signal processing system, 
<br>FFT/IFFT processor, and compressive sensing processor.
<br> 
<br>Text books：no
<br>Lecture Notes
<br>
<br>Reference：
<br>1. “VLSI Digital Signal Processing Systems – Design and Implementation,” by 
<br>Keshab 
<br>K. Parhi, Wiley Interscience.
<br>2. “DSP Architecture Design Essentials” by Dejan Markovic and Robert W. 
<br>Brodersen, 
<br>Springer, 2013   
<br>“Digital Signal Processing – A Practical Approach,” 2nd Ed. by E.C. Ifeachor and 
<br>3. B.W. Jervis
<br>4. “Multi-Rate Signal Processing for Communication Systems,” by Fredric Harris, 
<br>Pearson Education Inc. 2004. 
<br> 
<br>Teaching Methods: 
<br>Slides and Lecture Notes
<br>	
<br>Syllabus：
<br>Introduction   
<br>   1. DSP typical modules
<br>Part I: DSP Modeling and Optimization
<br>   2. DSP Modeling
<br>   3. Pipeline and Parallel Processing
<br>   4. Optimization
<br>   5. Systolic Architecture Design
<br>   6. Word-Length Optimization
<br>Part II: Circuit Design for DSP
<br>   7. Energy and Delay Models for Circuits Optimization
<br>   8. Energy and Delay Models for Architecture Design
<br>Part III: DSP Architectures
<br>   9. Arithmetic Operators
<br>   10. Digital Filter Architecture  
<br>   11. Multi-Rate DSP Architecture  
<br>   12. FFT/IFFT Processor 
<br>   13. Compressive Sensing Processor (optional)
<br>
<br>
<br>Evaluation:
<br>Homework (6 Paper Homework + 2 Verilog Labs)    60%  
<br>Final Project                                   20%
<br>Final Exam                                      20%
<br>
<br>Website: NTHU EEclass
<br>https://eeclass.nthu.edu.tw/course/9179
<br>
<br>修課前必備能力 Pre-requisites:
<br>1. Verilog HDL coding
<br>2. Digital circuit design and implementation in FPGA or IC
<br>3. Digital signal processing or Signal and Systems
<br>注意：本課程只適合具備以上能力與修習過相關課程之學生，上課不教授任何積體電路設計工具程式
<br>之技術。