1. Course Description
The objective of this course is to provide students an overview of VLSI designs,
particularly about how we manage to integrate billions of transistors to perform
complex functions. This course focuses on three major topics: logic design,
electronic design automation, and computer architecture. Students will learn the
layered abstraction of design technology from the ground up, including
combinational/sequential circuits, gate-level design, physical layout, micro-
architecture, and processor cores.


2. Teaching method
In-class lectures.


3. Syllabus
This course is partitioned into three parts for a sixteen-week semester, and each
part will have its own exam for evaluation.

Part 1. Logic design and hardware description language (HDL)
CMOS logic gates, combinational logic, CMOS latches and flip-flops, sequential
blocks, and memory.

Part 2. Electronic design automation (EDA)
Cell-based design, timing and power analysis, clock tree and power grid, floorplan
and routing.

Part 3. Computer architecture
RISC-V instruction set architecture (ISA), single-cycle processor, pipelined
processor, and memory hierarchy.


4. Evaluation (TBD)
Part-1 Exam (33%)
Part-2 Exam (33%)
Part-3 Exam (34%)


5. Website
eeclass.nthu.edu.tw


6. Reference book (not required)
CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition, Neil Weste,
David Harris, Addison Wesley, 2010
Digital Design and Computer Architecture, RISC-V Edition, Sarah Harris, David
Harris, Morgan Kaufmann, July 2021


7. Usage of generative AI tools
If report writing is assigned, generative AI tools are conditionally allowed if
the student clearly states how the texts are generated.