一、課程說明 (Course Description)

This course is to let students have hand-on experiences of modern
digital designs with the following topics:

- Introduction to the basic concepts in logic design that form the basis of digital computation and
communication systems.

- Verilog and FPGA implementations.
- Logic gates and memory elements.
- Timing methodologies. Finite state systems.
- Programmable logic.
- Basic computer organization.

二、指定用書 (Textbook)

There is no required textbook. However, we will provide the lecture
notes. In addition, the students need to possess backgrounds of basic
logic design concepts.

Prerequisite: Digital Logic Design or VLSI design.

三、參考書籍 (References)

To be announced.

四、教學方式 (Teaching Method)

Lectures and labs

Lab:
The students will have opportunity to write Verilog codes and test their
design on FPGA boards.
The lab hours is 3:30pm-5:20pm, Tuesdays; the class hours are 3:30pm-5:20pm, Thursdays.

Lectures:
The instructor will teach Verilog as well as basic concepts of Logic
Design, VLSI Design, Computer Architectures, as well as backgrounds on
programming and hardware implementation knowledge.

五、教學進度(Syllabus)

1: Gate-level modeling
2: Data-flow modeling and Behavioral modeling
3: Sequential circuits & FPGA board
4: Finite State Machines & FPGA board
5: Advanced circuit implementation, Finite State Machine, and FPGA board
6: Integration with different sensors and peripherals

Final Project: The students will submit a proposal, then exercise their creativity to
build a small course project.


六、成績考核(Evaluation)

Lab assignments, hand-on exams, final project.

七、可連結之網頁位址

To be announced (EECLASS).

八、使用 AI 的規則 (Rules of AI Tool)

(2)有條件開放,請註明如何使用生成式AI於課程產出
作業(問題回答和程式)不可以抄襲,包括使用AI生成工具,報告中文字可使用AI生成工具修飾,但需註明使用範圍和
方式。