● 課程說明(Course Desc<x>ription)
<br>The course is designed to provide the fundamental theories & techniques of digital 
<br>VLSI design in CMOS technology and carry out a digital VLSI deign. In this course, 
<br>we will study the fundamental knowledge of designing digital VLSI systems include 
<br>the operating mode of a MOSFET transistor and basics of MOSFET modeling, the 
<br>desc<x>ription of CMOS fabrication and design rules, the analysis of static and 
<br>dynamic behaviors of CMOS logic gates, the design of combinational logic and the 
<br>system-level circuits, the optimization concepts of circuit and layout designs. 
<br>Laboratory and project works will be utilized on industrial standard tools.
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<br>● 指定用書(Text Books)
<br>CMOS VLSI Design, a circuits and system perspective, Heil Weste and David Harris,
<br>published by Pearson, 4th edition, March 2010.
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<br>● 參考書籍(References)
<br>後補
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<br>● 教學方式(Teaching Method)
<br>Lectures offered in English
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<br>● 教學進度(Syllabus)
<br>1. Introduction 
<br>2. MOS Transistor Theory
<br>3. CMOS Fabrication, Layout and Modelling
<br>4. CMOS Inverter 
<br>5. Delay and Transient Response
<br>6. Power and Interconnect
<br>7. Design Margin and Reliability
<br>8. Combinational Circuit Design
<br>9. Sequential Circuit Design
<br>10. Datapath Subsystems
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<br>Lab:
<br>1. Cadence Setup and Schematic Entry
<br>2. Schematic Entry and Circuit Simulation
<br>3. Hierarchical Schematic Design
<br>4. Layout Editor and Design Rule Check
<br>5. Layout Versus Schematic
<br>6. Post-Layout Simulation
<br>Final Project: Logic circuit design (Simulation and optimization)
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<br>● 成績考核(Evaluation) (必填)
<br>Homework & Lab. Assignments: 30%
<br>Final project: 20%
<br>Midterm: 25%
<br>Final: 25%
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<br>● 採用下列何項 AI 使用規則 (Indicate which of the following options you use to 
<br>manage student use of the AI)
<br>禁止使用，請註明相關的監管機制 Prohibited use; please specify relevant oversight
<br>