一、課程說明(Course Description)

In this course, we study and implement a system with multiple cores and accelerators
with ESL environments (SystemC/TLM). We will also use High-Level Synthesis (HLS)
to design and synthesize RTL circuits from SystemC. The HLS-based design can be
integrated with a RISC-V virtual platform (riscv-vp) for hardware and software
co-design and analysis. We will use several examples including image processing
and deep-learning neural networks to investigate efficiency of different system architecture
with software and hardware components.

二、指定用書(Text Books)

自編課程講義，請參考以下書目或網頁連結。


三、參考書籍(References)

1. SystemC: from the ground up by David C. Black, 2010



2. TLM-2.0 Reference Manual



3. RISC-V VP: https://github.com/agra-uni-bremen/riscv-vp



4. Principles and Practices of Interconnection Networks, by William James Dally and Brian Towles, Morgan
   Kaufmann 2004.

四、教學方式(Teaching Method)

Lecture and lab practice.

五、教學進度(Syllabus)


週次 授課內容

1 Introduction to ESL

2 SystemC 1

3 SystemC 2

4 SystemC 3

5 TLM 1 (point-to-point)

6 TLM 2 (interconnect)

7 High-level synthesis 1

8 High-level synthesis 2

9 High-level synthesis 3

10 Midterm Demo

11 RISC-V Introduction

12 RISC-V Virtual Platform

13 RISC-V VP Software Integration and Multi-core Platform

14 Network on Chip (NoC) Introduction

15 ESP Platform

16 Final Project Dem


Lab 1 SystemC – Modules and Datatypes

Lab 2 SystemC – Process, Event, and Channel

Lab 3 TLM-2.0 Point-to-Point Connection

Lab 4 TLM-2.0 Bus

Lab 5 High-level Synthesis with Stratus

Lab 6 Pipeline and Parallelism with Stratus

Lab 7 RISC-V VP platform

Lab 8 Multi-core RISC-V VP platform


六、成績考核(Evaluation)


1.Homework 60%

2.Midterm Demo 20%

3.Final Demo 20%



七、可連結之網頁位址

(Notes) https://eeclass.nthu.edu.tw/

(Lab material) www1.ee.nthu.edu.tw/ee647000/

八、AI 使用規則 (AI Rules)

有條件開放，請註明如何使用生成式AI於課程產出 Conditionally open; please specify how generative AI will be
used in course output